digital-locker-verilog/Locker.v at main · Divyanshu-53/digital-locker-verilog · GitHub

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module Locker (clk,rst,datain,Enter,locked,unlocked);
input clk,rst,datain,Enter;
output reg locked,unlocked;

parameter idle = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter unlockstate = 3'b100;
parameter lockstate = 3'b101;
parameter errorstate = 3'b110;

reg [2:0] ps,ns;
reg [1:0] attempterr;

always@(posedge clk or posedge rst) begin

if(rst) begin  ps <= idle; attempterr = 0; end

else  begin
ps <= ns;

if(ps == errorstate) attempterr = attempterr + 1;

else if (ps == unlockstate) attempterr = 0;

end

end

always@(*) begin
ns = ps;
locked = 1;
unlocked = 0;

case(ps)
	idle : begin
			if(datain == 1 && attempterr < 3)
				ns = s1;
			else
				ns = errorstate;
			end
	s1 : begin
			if(datain == 0 && attempterr < 3)
				ns = s2;
			else
				ns = errorstate;
			end
	s2 : begin
			if(datain == 1 && attempterr < 3)
				ns = s3;
			else
				ns = errorstate;
			end
	s3 : begin
			if(datain == 0 && attempterr < 3)
				ns = unlockstate;
			else
				ns = errorstate;
			end
	unlockstate : begin
						unlocked = 1;
						locked = 0;
					if (Enter)
						ns = idle;
					else
						ns = unlockstate;
			end
	lockstate : begin
					locked = 1;
					unlocked = 0;

					if(Enter)
						ns = idle;
					else
						ns = errorstate;
					end
	endcase
	end
endmodule