Build HPC

Author: ElBi21

Extra/HPC/chapters/chap1_intro.tex

@@ -113,6 +113,7 @@ \section{CPU microarchitecture}
 \nwl
 Superscalar processors have the capability of issuing more than an instruction per clock cycle. The maximum number of instructions that can be executed in a clock cycle is called issue width.
 \nwl
+
 % {recover VLIW}
 In order to contrast static scheduling, CPUs use dynamic scheduling. For this kind of scheduling, CPUs employ:
 \begin{itemize}