Implementation of Basic Ciphers

Table of Contents

• Introduction
• Developer team
• Theoretical Description and Explanation
• Hardware Description of Demo Application
• Software Description
• Instructions
• Video
• Tools and References

Introduction

The objective of this project is to showcase elementary ciphers like the Vernam Cipher, Caesar Cipher and Adbash Cipher by employing fundamental logic gates and flip-flops on the Nexys A7 FPGA board. Through this setup, users can input letters in binary code and witness the resulting ciphertext generated during the encryption process for each cipher.

Developer team

Roman Štofa: tried programming but failed :(, prezentation, repository
Adam Hodor: programming, testing, top_level diagram
Dominik Rechtorík: programming, documentation
Dominik Šrenk: programming, repository, testbenches

Theoretical description and explanation

This project aims to demonstrate simple ciphers, in this case the Vernam Cipher, Caesar Cipher and Adbash Cipher using basic logic gates and flip-flops on the Nexys A7 FPGA board. Each cipher is enabling users to input letters in binary code and observe the resulting ciphertext generated by the encryption process. Buttons and switches serve as input devices for users to input letters and control the encryption/decryption process. The seven-segment display is used to show the binary code that we want to encode/decode and this encoded or decoded code can be seen in the Putty console on PC. We are connecting the board to the computer using the 6Pin USB TTL UART converter.

Hardware description of demo application

Nexys A7 50-T and its components

Nexys A7 50-T schematic

6Pin USB TTL UART converter, CP2102, DTR pin for Nexys A7 50-T board

Software description

This diagram depicts the utilized components and the significant data exchanges among them. The components are instantiated at the top_level.

Component: Caesar Cipher ^{source, testbench}

The input is given as "ahoj" (65 - a, 72 - h, 79 - o, 74 - j), the shift is set to 2, so when encoding, 2 is added to each letter and output as code_output (encoded message). Subsequently, code_output is transformed into coded_text_input, and the shift is subtracted from its values to produce decode_output, which is essentially the decoded output.

Component: Atbash Cipher ^{source, testbench}

Transforms A to Z, B to Y etc.

Component: Vernam Cipher ^{source, testbench}

The input is given as "ahoj", the shift generates random seed (in this case 00000011), so when encoding, input values are XOR-ed with shift value creating code_output (encoded message). code_output is transformed into coded_text_input, and the shift is again using mathematical function XOR to create decode_output, which is essentially the decoded output.

Component: 7-segment display driver ^{source, testbench}

This component acts as a driver for the displays: it maps binary numbers to individual segments. sig_clk_100MHz is set to 2 ms. The component has several inputs, including sig_data7 - sig_data0 and outputs sig_dig7 - sig_dig0 responsible for the position on the 7-segment display. sig_seg6 - sig_seg0 are used to illuminate individual segments. It uses a counter to cycle through these vector signals to select which one to display on each 7-segment display.

Instructions

BTNC - reset

BTNR - sends data from the board to the computer via a 6-pin USB TTL UART converter

BTND - stores data from the display as input into the component

SWL0 - encoding

SWL1 - decoding

SWL2 - Adbash cipher

SWL3 - Vernam cipher

SWL4 - Caesar cipher

SW[0:7] - sets 0 or 1 on individual digits

Ja-Pins(1) - serves to connect the board and the computer using the 6Pin USB TTL UART converter

Since we're writing letters in binary code, the ASCII table will come in handy.

Video

Videosák

Tools and References

Vivado Design Suite

VHDPlus

Nexys A7 reference manual

GTKWave

VHDL testbench generator

Draw.io

Digital Electronics Lectures presentation by Tomas Fryza