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    327 repositories

    • padrick

      Public
      Padrick - A Smart Pad-Multiplexer IP Generator for SoCs
      Python
      •
      Apache License 2.0
      •4•7•7•1•Updated Jul 24, 2026Jul 24, 2026

    • core-v-xif

      Public
      RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
      SystemVerilog
      •
      Other
      •31•0•0•1•Updated Jul 24, 2026Jul 24, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •50•163•3•17•Updated Jul 24, 2026Jul 24, 2026

    • redmule

      Public
      GEMM and GEMM-Ops accelerator for PULP systems
      SystemVerilog
      •
      Other
      •26•110•3•4•Updated Jul 24, 2026Jul 24, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •4•5•4•8•Updated Jul 24, 2026Jul 24, 2026

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •26•21•3•4•Updated Jul 24, 2026Jul 24, 2026

    • ManyRVData

      Public
      This is the repository for CachePool architecture for the ManyRVData project
      C
      •6•3•1•3•Updated Jul 24, 2026Jul 24, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •21•17•5•1•Updated Jul 24, 2026Jul 24, 2026

    • magia-sdk

      Public
      C
      •
      Apache License 2.0
      •11•6•8•13•Updated Jul 24, 2026Jul 24, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •112•355•23•30•Updated Jul 23, 2026Jul 23, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •27•36•4•7•Updated Jul 23, 2026Jul 23, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      riscvdebug
      SystemVerilog
      •
      Other
      •97•316•35•7•Updated Jul 23, 2026Jul 23, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •362•1.6k•50•17•Updated Jul 23, 2026Jul 23, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •11•38•1•2•Updated Jul 23, 2026Jul 23, 2026

    • control-pulp

      Public
      Open-source, hardware/software RISC-V platform designed for on-chip power control
      C
      •
      Other
      •4•9•1•3•Updated Jul 23, 2026Jul 23, 2026

    • softhier-sdk

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Jul 23, 2026Jul 23, 2026

    • spatz_vpu

      Public
      Spatz vector processing unit
      C
      •
      Apache License 2.0
      •0•0•0•1•Updated Jul 23, 2026Jul 23, 2026

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •381•9•0•4•Updated Jul 23, 2026Jul 23, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •61•323•3•4•Updated Jul 23, 2026Jul 23, 2026

    • llvm-project

      Public
      C++
      •18k•15•7•1•Updated Jul 23, 2026Jul 23, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •62•379•27•14•Updated Jul 23, 2026Jul 23, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •130•255•3•9•Updated Jul 22, 2026Jul 22, 2026

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •9•38•0•2•Updated Jul 22, 2026Jul 22, 2026

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •45•93•2•4•Updated Jul 22, 2026Jul 22, 2026

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •38•141•4•8•Updated Jul 22, 2026Jul 22, 2026

    • ace

      Public
      SystemVerilog
      •
      Other
      •7•26•0•1•Updated Jul 22, 2026Jul 22, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •7•23•20•0•Updated Jul 22, 2026Jul 22, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •202•768•7•1•Updated Jul 22, 2026Jul 22, 2026

    • pulp-linux

      Public
      Build GNU/Linux for various PULP/Cheshire-based systems.
      C
      •1•4•4•0•Updated Jul 22, 2026Jul 22, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •111•139•18•2•Updated Jul 22, 2026Jul 22, 2026
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